Digital PLL Research Work

A New Digital PLL at the Technische Universitaet Berlin

The Cooperation Project

The cooperation project between the Technische Untiversitaet in Berlin, Germany the compound semiconductor group of Motorola, Phoenix, and Cascade Design Automation, Seattle focussed on fully digital high speed clock generators for GaAs microprocessors, DSPs and synchronous logic in general.

In a prototype design clocks generated by a fully digital PLL sped up a hard coded DSP for ultrasonic materials testing applications.

The Target

Key feature of this design is an unprecedented full digital PLL implemented in GaAs. Amoung its many advantages over conventional PLL (even those considered 'digital' are :

Completely digital. Can be implemented in 100% digital fab technology

No influence on performance due to Process variationswithin large security margins

Portable to CMOS technology. (Allready silicon proven)

Achieve lock withing 3 cycles of input clock

Keeps lock even during rapid changes of input clock

The Results

Analysis of the generated clock at 500MHz show high speed capture and stability of frequency in spectral composition.

The Chip

Researchers at the Institute for Microelectronics at the Technische Universitaet of Berlin have implemented the digital PLL as a module in the materials testing chip as well as a stand alone chip for clock generation purposes.

The Ultrasonic Echo Analysis Chip

The Stand Alone Digital PLL

The Digital PLL Performance

The same digital PLL runs in both chips. The following table summarizes some features of the design:

Performace data of the digital PLL
Name	Units	Value
Input freq. range	MHz	60-150
PLL multiplication factor	x	5
Output freq. range	MHz	300-750
Edge slope (rise/fall)	V/s	$6,46 10^9 / -4,42 10^9$
Chip area (incl. pads)	$mm^2$	3,257 x 3,281
Power consumption @2V VDD (incl. Pads)	W	3,07

The Tools

The design took two researchers three months to design from scratch. The Cascade GaAs library of standard cells were used for the core logic and for the I/O ring. The design was floorplanned and routed using Cascade tools. Static timing analysis was also completed using Cascade tools.

The Future

Research in the field continues in close cooperation with Cascade Design Automation. Students are working towards their graduation on optimization startegies of the design. Next steps will be maximum output freuqncies above 1GHz and research towards implementing the PLL as a macro cell into the Cascade library environment.