The demands of new higher speed processors and parallel processing has made memory throughput (bandwidth) a bottleneck in modern computer systems. Memory interleaving is a technique implemented to increase the maximal throughput of data a memory system can provide per unit time. However, memory interleaving does not effect memory latency as discussed in the cache section.

Memory interleaving is implemented by dividing the memory system into a number independent banks which can answer read or write requests independently, in parallel. For example the Intel Orion 450GX chip set (discontinued) for the Intel Pentium Pro processor used four-way interleaved memory by dividing its memory into four banks. The most extreme interleaved design is used in current SMP vector supercomputers (Cray) which may have up to 256 way interleaved memory banks!

In a typical four-way interleaved memory system the SIMM's are divided logically into four banks. When lines of data are written to the memory four lines of data may be written simultaneously because each line can be written to each bank separately, in parallel. In contrast, in a non-interleaved system only one line may be written to memory in the same amount of time. Therefore four-way interleaved memory can read and write data four times faster than non- interleaved memory at its maximal rate. Imagine what a 256 way interleaved memory supercomputer can do! You may want to note that this technique of interleaving is analogous to disk striping in a RAID system (see our hard drive technical section) and increases through put in the same manor.

To obtain the maximal throughput of interleaved memory the data must be prefetched. Prefetch techniques are automatically utilized by pipelined and superscalar CPU's. The use of Prefetch loops is particularly important for iterative loops like "for (i=1; i&ltn; i++) { ... a[i] ... }." Where the CPU must Prefetch elements of a[i] from memory before they are actually called for. Problems are also encountered in matrix and vector math when an operation requires access to data in a sequence that is some multiple of the interleaving. In this cases all the data needed is in the same memory banks. However, modern compilers, especially Fortran compilers will address such issues for the programmer.

Most PC chip sets like the Intel Triton-II (430HX and 430VX) and the Intel Natoma (440FX) do not support memory interleaving because Intel does not believe PC users saturate their memory bus. However, many number crunching applications do saturate the memory bus. Increasingly Multi-processor PC's are being used for such applications and we hope to see future Intel Chip sets support memory Interleaving. We hope you send your thoughts on this to Intel. (Hint).

The Clock Cycle Time:

A computer sequences its tasks based on an oscillator which is basically a clock. The faster the clock runs, the faster the tasks get done. The speed of the clock is measured by its frequency in MHz (Millions of cycles per second). Computers based on the 440BX, 440GX and 440NX PCIsets have a bus speed of 100MHz. This means the bus oscillates 100,000,000 times per second. The duration of a single oscillation is known as the Clock Cycle Time (tCK). Clock cycle times are measured in nanoseconds. 1 nanosecond (ns) = 10e-9 or 0.000000001 seconds or one billionth of a second. tCK is given by the inverse of the frequency (tCK = 1/frequency). A 100MHz oscillator gives a 10ns clock cycle time.

Therefore, the Intel PC100 Specification requires a maximum value of 10ns for tCK. A Clock Cycle Time of 8ns is currently the fastest available. 8ns modules do not necessarily perform faster than 10ns modules on a 100MHz bus. Performance is based on a number of factors that will be described below. However, 8ns modules are capable of running on a 125MHz bus and are therefore of interest to over clockers.

Programming SDRAM modules with SPD EPROM's, BIOS settings and 3-2-2 notation:

SDRAM ICs are programmable. Values for programmable parameters are stored in the IC's Mode Registry at boot time. These values are set in a programmable register in the SDRAM IC which is set at power-up and remains set until the system is powered off. Programmable parameters include the Burst Mode, the CAS Latency (CL), the RAS Precharge Latency (tRP) and the The RAS to CAS delay (tRCD). Values for these attributes are read from the SPD EPROM on the module (See the SPD EPROM section) by the BIOS. The BIOS may use the SPD values, or the values may be overridden depending on the settings in your CMOS setup program. The final values are recorded in the 440BX registry. In a section below we document how to read these values from the 440BX registry.

In most cases these values must be overridden because the values in the SPD EPROM are incorrect. This is because the value of many parameters is dependent on bus speed. Since PC100 SDRAM may be used on boards with a 66MHz bus as well as boards with a 100MHz bus, the values stored in the SPD will frequently be set for the wrong bus speed.

In the Award BIOS you can find these settings in the "Chipset Features Setup." Change the "SDRAM Configuration" value from "By SPD" to "Disable." You can then set the respective values of "SDRAM CAS Latency," "SDRAM RAS to CAS Delay" and "SDRAM RAS Precharge" to the values of CL, tRCD and tRP respectively. In the CMOS setup these values are recorded as by values of clock tics denoted by 2T or 3T.

These three values, CL, tRCD and tRP, are often quoted with the notation 3-2-2 referring to tCL-tRCD-tRP. This should not be confused with burst timing notation as described elsewhere on this page. A value of 3-2-2 is optimal for current PC100 SDRAM on the market. 2-2-2 PC100 SDRAM has only been produced in low yields as described above. Module tolerances of 3-2-2 and 2-2-2 are most common. However, the Intel PC100 specification allows for a variety of tolerances ranging from 3-3-3 to 2-2-2.

Frequently a fourth parameter is referred to as the "DRAM Idle timer" in the BIOS. This is also known as the RAS cycle time (tRC). In the PC100 SDRAM specification this has a maximal value of 8. In an alternate notation 3-2-2 modules with a tRC of 8 are referred to as /3/2/2/8. The minimum standard for PC100 SDRAM is 3/3/3/8.

The operation of SDRAM in relation to latency:

We have already covered topics relating to refresh and latency above. We have defined the RAS Cycle (tRC), the RAS Precharge Cycle (tRP), tRAS, AUTO REFRESH and AUTO PRECHARGE as well as the impact of continuous reads or writes versus short reads and writes on these parameters. Now we can look more closely at the process of activating a bank and reading or writing data to that bank.

As discussed previously, commands and data addresses control access to banks of data. Commands are issued by holding the voltage low or high across several leads. Four very important leads are CS#, RAS#, CAS# and WE#. When CS# is high the other three leads are ignored. When CS# is held low t e voltages across RAS#, CAS# and WE# determine a set of commands used to manipulate the bank in question.

To access data an address must be setup before the clock by about 1 clock cycle (tAS). Then the ACTIVATE (RAS) command must be executed on an idle bank to put it in an active mode. A READ or WRITE (CAS) command is issued after the ACTIVE (RAS) command. The period between the ACTIVE command and the subsequent READ or WRITE command is the RAS to CAS delay (tRCD).

Data is read out sequentially, synchronized with the positive edge of CLK. Data is sequentially bursted according to the burst mode set in the Mode Registry. The burst mode may be set to 2, 4 or 8 words or even to a full page (the entire column). The initial data from the READ command is available (data out) after a period equal to the value of the the CAS Latency (CL) as set in the Mode Registry.

Therefore the total access time to the first data word is generally equal to tAS + tRCD + CL. This may be something like 1+2+3 = 6. Subsequent data is bursted out synchronous with the clock at one clock per word for the duration of the burst mode.

As noted above the PC100 specification requires a minimum standard of 3/3/3/8. The specification also requires a 6ns or less Access Time from Clock (tAC 6ns). tAC is basically the time in nanoseconds for data to be read.

Most PC100 modules have a CL of 3. The Samsung -GH and Micron -8D and -8E have a CL of 2. Modules with a CL of 2 are difficult to produce in ample yields and are therefore much more expensive than modules with a CL of 3. The lower CL only increases total SDRAM performance marginally (~5%) and therefore are considered to offer too little bang for the buck. However, CL 2 modules are of some interest to those who over clock their systems to bus speeds of 112MHz. We do not suggest over clocking the bus speed. However, we do carry the faster modules for those who are interested in them.

The values listed in specifications may be confusing because they are alternately listed in clocks tics or nanoseconds. For example, the RAS to CAS delay, tRCD, is the number of clock cycles allowed between the ACTIVATE (RAS) command and the READ (CAS) command. The value of tRCD is generally 20ns or 30ns (2 or 3 clocks). The value of the tRCD latency in nanoseconds may be divided by the bus speed in nanoseconds (100Mhz is 10ns) and then rounded up to the nearest whole clock value. For example a tRCD of 20ns would yield a latency of 2 clocks cycles (20ns / 10ns). The RAS Precharge (tRP) is typically 20ns of 30ns. (tRP is analogous to the CAS# before RAS# (tCBR) described above for EDO RAM).

We have found that the values set in the SPD are frequently incorrect. Indeed, it is not possible to set these values correctly for all bus speeds. These values should be overridden. Lets look at CAS latency (CL) as an example. Recall That CL is the time from the READ command to the first data out. If a module is rated as 3/2/2/8 (which most are) to what value should the SPD CL be set? Suppose the module is used on a 440BX board with a 333MHz CPU. The bus speed would be 66MHz which has 15ns tCK. A 3/2/2/8 modules has a CL of 30ns. Therefore on a 66MHz bus the CL should be set to 2 (30ns/15ns) in the SPD. Suppose the same module is used on the same 440BX board with a 400MHz CPU using a 100MHz bus. The bus speed would be 100MHz which has 10ns tCK. A 3/2/2/8 modules has a CL of 30ns. Therefore on a 100MHz bus the CL should be set to 3 (30ns/10ns). To which value should this module's SPD be programmed? 2 or 3? There is no correct answer. It doesn't appear that Intel took this into account when writing the specifications of the SPD. In actual practice you'll find SPD set to very odd values indeed. Therefore, override these values in your BIOS and set them up by hand the old fashioned way. Generally you'll set these values to 3/2/2/8.

What happens if you don't set the module parameters correctly? If you set the parameters to conservatively your system may perform about 20% too slow. But no other harm will be done. If you set your module parameters too fast, you will not damage the module nor the motherboard. However, you will end up with data corruption. This corruption may be insidious and difficult to detect at first. But eventually it will catch up to you. To test for data corruption try unpacking large software packages like the entire X Windows system and running check sums. This seems to be a fairly good test for this type of data corruption.

Reading your register settings under Linux:

Register values for the 440BX PCIset are listed in the 440BX Specification in section 3.3. 3.3.24 lists the values for tCL, tRCD and tRP. A 16 bit address under control register 0 (Device 0), at address offset 76h77h defines these values. The default value is 00h. The three least significant bits are defined such that:

Bit 0:
SDRAM RAS# Precharge (tRP). This bit controls the number of DCLKs for RAS# Precharge.
0 = 3 clocks of RAS# Precharge.
1 = 2 clocks of RAS# Precharge.

Bit 1:
SDRAM RAS# to CAS# Delay (tRCD). This bit controls the number of DCLKs from a Row Activate command to a read or write command.
0 = 3 clocks will be inserted between a row activate command and either a read or write command.
1 = 2 clocks will be inserted between a row activate and either a read or write command.

Bit 2:
CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled by the SDRAMs and when the 82443BX samples read data from the SDRAMs. If a given row is populated with a registered SDRAM DIMM, an extra clock is inserted between the read command the when the 82443BX samples read data. For a registered DIMM with CL=2, this bit should be set to 1.
0 = 3 DCLK CAS# latency.
1 = 2 DCLK CAS# latency.

If you wish to read the values of these bits you can download and run 440bx.c. Compile 440bx.c with "gcc -O -c timing timing.c." The program will dump the bit values of address offset 76h of device 0. For example, a board set to 3-2-2 would read something like:

*** 440BX SDRAM Memory Timing ***

CAS# Latency: 3 DCLKs
RAS# to CAS# Delay: 2 DCLKs
RAS# Precharge: 2 DCLKs

Comparing Various ICs of PC100 SDRAM:

Typically the suffix on the chip part number can be used to compare various modules. However, with the recent hype of PC100 SDRAM, misleading markings have appeared that have confused end users. The following tables compare various models currently marketed as PC100. Note also that according to our tests, modules with identical specifications may actually perform quite differently. See our data on the 440BX Page.

SAMSUNG

TOSHIBA

LGS

* Note that the LG RAM -7J is a 10ns Cycle Time

MICRON

See also Information at Corsair.

The Quality of the Module:

The timing specifications of various ICs should not be the only factor that you use to choose a module. The quality of the module can frequently have a greater impact on the actual performance of the module than the ICs used and their respective specifications. Variation in the length, width and depth of traces as well as the placement of traces can profoundly impact performance. Moreover, the proper quality of source resister packs must be used to cancel reflected signals. The type of PCB can even effect performance. In sum, many factors can influence the quality and timing of signals sent from the IC to the bus especially with the tight tolerances required for PC100 complient modules. Selecting a good quality module in many cases is more important than the choice of chip.

Learn more about PC100 SDRAM performance on our 440BX Page.

The speed of the RAM is measured in nanoseconds. 1 nano-second (ns) = 10e-9 or 0.000000001 seconds or one billionth of a second. RAM is typically 60 or 70ns. However, the actual speed is generally a little better than the rating. If you look at your SIMM there is a serial number on each DRAM chip. The last digit is either a 7 or a 6 which references the speed of the SIMM as 70ns or 60ns respectively. Now you know how to read the speed of the SIMM.

The important thing to remember is that if you don't want wait states you need to buy 60ns RAM if memory bus speed is 66MHz and you can use either 60ns or 70ns RAM if your memory bus speed is 60MHz. The bus speeds for several processors are listed in the table below.

A computer sequences its tasks based on an oscillator which is basically a clock. The faster the clock runs, the faster the tasks get done. The speed of the clock is measured by its frequency in MHz. Time=1/frequency for example a 1000MHz oscillator gives a 1ns clock cycle. A 100MHz oscillator gives a 10ns clock cycle. However PC's divide the clock frequency by two. So a 66MHz PC uses a frequency of 33MHz which give you a 30ns clock cycle. The clock cycle is called the T state and everything happens as a multiple of on T state. A single read or write to memory takes 2 T states or 60ns. If the read or write can not be accomplished in 2T states, an extra T state (a wait state) is added. Adding a single wait state to a 2T state process leads to a 50% performance loss!

DRAM memory has very high latency compared to present day CPU speeds. The latency is the time for a memory module to respond to a read or write request from the CPU. For example a Pentium Pro CPU operating at 200MHz can issue transactions every 5ns (1/200,000,000). In comparison DRAM memory can only respond every 60ns's. For this reason, SRAM (Static Random Access Memory) with speeds typically ranging from 7 to 15ns is used between the CPU and RAM as a buffer or so called cache.

SRAM, like DRAM, is another type of volatile memory which can retain its data without refresh as long as electrical power is supplied. It is generally much faster than DRAM and generates zero wait sates. DRAM is cheaper because it requires only two transistors per bit, while SRAM requires 6 or 8 transistors per bit.

Cache SRAM is used to hold data the processor needs right away. Statistical analysis of modern computers shows that generally 90% of the data needed by the CPU is in the cache - this is called the hit ratio. If the CPU finds the data it needs in the cache it is called a hit, otherwise it must than seek the DRAM and this is called a miss.

Because cache SRAM memory is faster than DRAM memory, the hit ratio is proportional to the effective latency of the memory architecture. If we call the cache hit ratio H, and the latency of the cache and DRAM Tc and Tm respectively, then the effective (average) latency of a memory architecture with cache is given by:

Teff= H * Tc + (1-H)*Tm

The increase in speed due to cache is the ratio of Tm to Teff and increases exponentially with H:

S=Tm/Teff = 1/(1-H(1-Tc/Tm))

In order to achieve such a high efficiency or hit rate the cache must transfer only the most crucial data from the main memory to itself. This is accomplished by cache mapping techniques. The most important cache mapping technique is set associative cache mapping. However, this is very complex and in order to understand it you must first understand direct mapping and fully associative mapping.

The simplest form of mapping is direct mapping. All the data in the memory and cache is organized into logical blocks called cache lines. Data is transferred from the memory to the cache in cache lines. A cache line generally contains four words. A word in generally 32 or 64 bits of information. However, the cache can only hold a fraction of the cache lines held in the main memory. If we express the number of words in the cache memory as 2^a and the number of words in the main memory as 2^b then the fraction of data held by the cache is 2^a divided by 2^b or 2^(a-b) where a < b.

The data in the memory are broken into what are called equivalence classes. Each equivalence class is composed of 2^(b-a) elements or cache lines. For each equivalence class in the main memory there is an index plus a cache line in the cache. When the CPU seeks the cache for data is looks for the proper equivalence class and index in the cache. If this equivalence class holds that proper cache line there is a hit. If not it increments the index and pulls the proper cache line from the main memory and this cache line plus its index replaces the existing equivalence class and index in the cache memory.

This is conceptually the simplest form of mapping and it yields very fast access. For example, because each cache line is composed of four words. If several consecutive words are sought by the CPU than a cache miss will only occur once every forth word. However, if any iterative process seeks words in multiples of four it will cause continuous cache misses just as in memory interleaving. This will also cause much unnecessary traffic. Hence the hit ratio is poor and not very efficient.

The fully associative cache improves on the direct mapping by allowing cache lines and tags to be placed anywhere in the cache from main memory as needed. The fully associative cache mapping technique often uses a least recently used (LRU) strategy. When a cache miss occurs cache lines are brought from main memory and they replace cache lines that have been least recently used. Thereby any data that has not been accessed recently (and therefore presumably will not be accessed in the near future) will be replaced by neighbors of recently sought data. It therefore significantly improve the hit ratios.

The main memory contains 2^a words total and these words are broken into cache lines of 2^d words each. This means that there are 2^a divided by 2^d cache lines or 2^(a-d) cache lines. The cache contains 2^b total words with cache lines of 2^d words each also. Each cache line in the cache has a tag of (a-d) bits to specify its memory address.

However, this makes searches very expensive. In an associative cache, 2^(a-d) lines must be searched to determine if an address is cached. With a cache hit only the last d bits of the tag address needs to be used to find the address in the cache - otherwise the whole address of the tag can be used to find a miss in the main memory.

In a direct mapped cache we have a well indexed and easy to search data set in the cache. The data in the cache corresponds nicely with the data set in the RAM. However, most of this cached data is useless, yielding a high miss rate. In contrast, the fully associative cache has a lot of data that we need because the data is filled in using LRU. However, it is disorganized and searching its tags is a huge tour of force.

Enter the set associative cache! It combines the organization of the direct mapped cache with the high hit rate of the fully associative cache. A new parameter, k, is defined such that all the 2^(a-d) cache lines are indexed into 2^k elements called the associativity of the cache. Each element is easily found just like the direct mapped cache. Within each element are 2^(a-d-k) sets of cache lines. Each element uses associative addressing so that only 2^k comparisons are necessary per addressing operation.

So a set associative cache is just a set of fully associative cache indexed in the larger more organized infrastructure of the direct mapped cache. Put another way, if k=0 (each set has one cache line) we have a direct mapped cache. If the number of sets equals one we have a fully associative cache.

Hence modern computer systems are able to achieve extremely high hit rates of approximately 90% using the set associative cache.

Burst timing expresses the number of clock cycles it takes to read or write a cache line of data from a source to a destination. Generally a cache line is composed of four words of data, called dwords. So the burst timing expresses the number of clock cycles it takes to read or write each of these four words from a source to a destination. The source and destination can be the processor, the RAM, or the L2 cache.

The first word always takes more clock cycles to read or write. This is because the entire memory address of the first word must be sent wile the next three words are automatically bursted out as the memory logic increments the internal address pointer.

Burst timings are recorded in notation like 5-2-2-2. In this example the first word of the cache line takes five clock cycles and remaining three words take two clock cycles each. The transfer of all four words takes eleven clock cycles.

Different types of RAM have distinct maximal burst rates. I say maximal because the motherboard's chip set must support these burst rates for them to be utilized. Not all chip sets support higher burst rates. When you buy a new mother board it is important to look at the burst timings the chip set can support and pick RAM and cache that fully uses the maximal burst rate. Here are some characteristic maximum burst rates for different types of RAM and the CPU. Note that at higher bus frequencies burst rates slow down:

For EDO RAM on a Triton-II (430HX) chip set, it is common to see burst rates like 5-2-2-2. Pipeline burst cache is much faster and can achieve burst rates 3- 1-1-1. In modern motherboards the burst rates are auto-detected by the BIOS. However, there is generally a screen in the CMOS Setup that allows you to override the defaults and change the burst timings. This may be useful if you are getting page faults or random lock-ups and you want to slow down the burst rates. However, this is probably a sign of a problem with your system. I've also had clients that have jumped into the CMOS setup and manually set the burst rates as high as possible. Then they wonder why their system is crashing all the time. Don't do that! You will corrupt your data and suffer intermittent crashes. Let your system run as it was designed.

The Intel Pentium and Pentium Pro CPU's can achieve a maximal burst rate of 2-1-1-1. In order to keep the system from experiencing wait states the cache must be able to supply data to the CPU with a 2-1-1-1 burst timing. Pipeline burst SRAM comes close to doing this as it burst at 3-1-1-1. However, when there is a cache miss the Main Memory must be accessed which means the burst rate falls all the way down to 5-2-2-2 in the case of EDO DRAM. Therefore larger caches are crucial to multi-tasking operating systems that have large memory requirements.

The table below shows the burst timings of various types of cache at various bus speeds. The shaded region indicates the best price per performance at a given bus speed. Since present motherboard bus speeds range from 50 to 66MHz, the best cache to use would be Sync Burst SRAM. However, Sync Burst SRAM has never been brought into full production so Pipeline Burst SRAM is used instead. Note that Sync Burst SRAM can achieve burst rates of 2-1-1-1 which is the same as the CPU so it can actually support zero wait states.

Older PC's used Asynchronous SRAM which had a maximum clock-to-data times of 15ns. However, at higher bus speeds Asynchronous SRAM generates very slow burst timings. New technologies including bursting, pipelining and synchronization with the system clock have increased maximum clock-to-data times to less than 6ns while maintaining good burst timings.

Synchronous DRAM is synchronized to the system clock and all signals are triggered on a clock edge. Very few systems support Synchronous DRAM. Burst capability, as described by burst timings, is the capacity of the RAM to auto- increment its address pointer and retrieve four words of data at a time. The first word takes longer to find, but once the absolute address is found the pointer logic incrementally adds three sets of words to the address and downloads the following three words in anticipation that the program will ask for this sequential data next. Pipelining is an architecture analogous to an assembly line. Data can be passed through a multi-staged pipe. Each stage of the pipe performs a different task. In this way several pieces of data can travel down the pipe like cars on an assembly line. In the case of Pipelined Burst SRAM input or output registers are added to the cache so that one set of registers can start to read new data while current data can be written. The register loading slows down the cache a little but this is more than offset by the ability to overlap the read and write tasks of different cache lines.

Data in memory may be shared by a variety of processes at the same time. This saves memory and increases the system speed. This is quite common on today's multi-tasking PC's that implement implicit parallel processing in the superscalar design of their CPU's and explicit parallel processing by using mgltiple CPU's. For this reason cache is extremely important and in extreme cases computers have been designed like the KSR have a cache-only memory system, in which the global memory is just a collection of all the caches used for each processor.

For data that is read only shared memory is fairly simple to implement. However, if data that is shared by several processes is written to and altered it can cause consistency problems. Care must be taken that altered data is written back to main memory. In systems using write through cache whenever a write occurs it is simultaneously written to the cache and the main memory. Alternatively a write-back system writes data to the cache and then marks it with a dirty bit. It is then written back to memory from the cache only when space is needed in the cache for further data.

Cache has to be mapped to cover all of your RAM. That's were the tag chip comes in. The tag chip determines how the cache maps to the memory. If you have more than 64MB's and you want to cache beyond 64MB's you must have a tag chip that supports this. Most tag chips only allow for caching of the first 64MB's. Newer versions of cache have two tag chips and can be jumped to cache either up to 64MB's or RAM or 128MB's of RAM. However, older chip sets like the Intel Triton-I (430FX) can not support caching above 64MB's. This is because Intel does not believe PC users need more than 64MB's of RAM. We encourage you to send you comments about this to Intel (Hint). Some newer chip sets like the Intel Triton-II (430HX) support caching more than 64MB's of RAM as long as you have two tag chips.

New versions of SRAM cache are packaged in COAST's (Cache On A stick) and fit in a CELP (Card Edge Low Profile) socket. It is very important to get the proper Cache module version for your mother board or you'll get page faults and random crashes. COAST 1.2's only work on older Triton I boards. COAST 1.2's have low shoulders near the pins measuring 0.295 inches. COAST 2.1's or later work on all current motherboards and support global writes. These COAST's have high shoulders near the pins measuring 0.492 inches. COAST's with uneven shoulders should only be used with 430VX boards. Don't confuse COAST version number with the chip version number sometimes printed on the COAST.

There are several alternate SIMM architectures available. These include the standard fast page mode (FPM) DRAM, Extended Data Out DRAM (EDO), Burst EDO (BEDO), Synchronous DRAM (SDRAM), GRAM (synchronous graphics RAM), EDRAM (enhanced DRAM), CDRAM (cache DRAM), MDRAM (multibank DRAM) and RAMBus. Relative burst rates for some of the more important RAM types are listed above. Page mode was the earliest type of RAM and has since been replaced by FPM. Only recently has FPM be virtually replaced by EDO. Now SDRAM looks like it will take the place of EDO according to many experts.

As discussed earlier FPM DRAM is simply a bunch of capacitors arranged in rows and columns. A single row is accessed by lowering the RAS (Row Access Strobe) for that row. Then cycling CAS (Column Access Strobe) accesses consecutive columns of data one after the other. A low CAS allows data to be accessed. A high CAS locks the data and moves to the next column of data. In the case of EDO RAM a high CAS does not lock the data, instead a so-called data latch is used which is independent of CAS. So CAS can continue on to the next column before all the data from the current column is read. So reads in EDO can overlap and the CAS cycle is 20-25% faster. This yields faster burst timings for EDO. However, the system speed improvement is only about 1-2% because most data access still goes on in the cache since EDO DRAM is still much slower than SRAM. EDO RAM will probably have a limited life span if Bus Speeds continue to increase beyond 66MHz.

BEDO is another alternate architecture which has not been released yet. EDO RAM will work with older FPM style motherboards as long as they don't attempt to interleave the memory in FPM mode. BEDO is the same as EDO except it has an optimized burst address mechanism and it pipelines the latch system. Burst capability, as described by burst timings, is the capacity of the RAM to auto- increment its address pointer and retrieve four words of data at a time. The first word takes longer to find, but once the absolute address is found the pointer logic incrementally adds three sets of words to the address and downloads the following three words in anticipation that the program will ask for this sequential data next. Pipelining is an architecture analogous to an assembly line. Data can be passed through a multi-staged pipe. Each stage of the pipe performs a different task. In this way several pieces of data can travel down the pipe like cars on an assembly line. In the case of BEDO RAM input or output registers are added to the latch mechanism so that one set of registers can start to read new data while current data can be sent to the gate and forwarded to the CPU. The register loading slows down the latch a little but this is more than offset by the ability to overlap the reads on the data queue. However, like EDO its lifetime is limited by the fact that it can not exceed 66MHz bus speeds. Therefore BEDO may never become main stream.

Synchronous DRAM is synchronized to the system clock and all signals are triggered on a clock edge. SDRAM is faster than EDO and it works at bus speeds of up to 100MHz. However it currently works with the Intel 430VX chip set which is an extremely slow chip set because it shares its memory bus with the video card. The 430VX chipset is designed for low end computers.

• TI SDRAM
• Micron SDRAM
• Kingston's Online Ultimate Memory Guide

For a decade RAM prices have fallen in cycles. Over the long term RAM prices have continuously dropped as production has increased in the Asian Pacific RIM. The drops have been somewhat cyclical occurring in 1986-7 1991-2, 1996 the spring of 1999 and the first quarter of 2000. There is no reliable way to gauge the short term RAM market. However, understanding some of the factors involved may aid in your purchasing decisions. According to industry analysts RAM prices will go up from the second quarter of 2000 through 2001.

From 1995-1997 supply and demand made for a volatile market. Through 1995 RAM prices remained high due to several factors. Because of the booming 1994 computer market chip market analysts predicted huge demand for RAM in 1995. Hence huge inventories were produced. However, the 1995 computer market was soft. This was in part due to Intel's fast pace of CPU introduction and price drops. In addition the introduction of Win95 was expected to cause greater consumption of RAM as computer uses upgraded to the new OS. However, Microsoft only sold half as many licenses as expected. Furthermore several large computer manufacturers, like Compaq, over-stocked RAM in anticipation of a bull computer market in 1995 and to insulate themselves from RAM shortages and rising prices. Indeed, even Intel stocked huge amounts of RAM as it plotted to take on its own resellers head on by producing its own PC's. The demand for RAM caused by these companies was misinterpreted by RAM manufacturers as a increased need for RAM by the end user (when actually the RAM was just getting stock piled). The RAM manufacturers invested in more fabrication plants and increased production levels causing even more excess inventory. Since many of the large purchasing decisions where made up to a year in advance, there was no immediate feedback in the market and prices continued to rise. Finally prices soured as Sumitomo, Japan's resin plant suffered a fire. This plant formerly supplied two thirds of the resin used in encapsulating RAM chips. The rapid increase in prices further augmented investments in new fabrication plants.

Once the sales pipeline was filled to capacity with RAM it finally became clear that RAM supplies were far in excess of demand and the cost started to slip. In addition several new plants in the far east were producing RAM at prices lower than ever before. These plants focused on producing chips used in 16 and 32MB SIMM's which could be produced at the same price as the chips used in 4 and 8MB SIMM's (although with a higher failure rate). This began a price war between the 4MB SIMM's and the larger SIMM's. Slipping prices spooked Intel and other computer companies to dump their massive stock piles in Spring of 1996 hence causing a sudden crash in RAM prices. Since then several manufacturers in the US like Micron and several overseas chip manufacturers have put their plants on mothballs asserting profit margins were too low to continue production. Kingston finally sold its plants to the Koreans and dropped prices. Further the production of EDO RAM clearly pushed down the value of stocked FPM RAM.

RAM Prices rose dramatically in September 1996, as larger computer manufacturers like Compaq sucked the market dry. Increased demand was in part due to the release of Windows NT 4.0 and in part due to the rise of the book to bill ratio and seasonal stock piling in preparation for the holiday season.

RAM prices then dropped gradually with some volatility along the way until late January 1997. At that time prices rose slightly due to the increase demand for PC's after Intel's price drops. From 1997 until the Spring of 1999 RAM prices decreased due to oversupply. 

Memory prices hit an all time low of $4 per 64Mbit IC back in May of 1999. The price went up to $7 in June and $14 by the end of August. In September prices ranged from $15 up to $17 and hit a peak of around to $20 per IC in October 1999.

There were three catastophic events in Taiwan that affected pricing in August of 1999. Prices increased due to two earthquakes in Taiwan (6.7 and 6.9). This news followed the loss of f 15 million dollars worth of SDRAM, including 1.5 million 64Mbit ICs due to a substatial Taiwanese power outage which interrupted the curing process. However, Taiwan accounts for a little over one tenth of the total RAM market so the impact of these events are small compared to market forces.

Many factors affected the price of SDRAM. To a large part the higher pricing was due to demand outstripping supply. There had been a great increase in demand in Asia due to the recovery of local Asian economies. Globally there had been increased spending on new hardware in preparation for Y2K. Moreover, there was a seasonal increase in demand for products in September that normally lasts through the winter months. Shortages have affected not only the SDRAM market but also many other components.

The supply of 64Mbit ICs used in 64MB, 128MB and 256MB SDRAM modules had been decreased. 64Mbit ICs had been selling at a loss for a long time. Therefore many manufacturers had been switching production to 128Mbit technology and had been ramping down production of 64Mbit ICs.  For example, in August, one of the major producers of 64Mbit SRAM, Samsung (Korea), announced they were closing most of their 64Mbit fabs. TI jumped out of the RAM market and sold their fabs to Micron. This lead to the normal price increases associated with supply and demand.

From November 1999 until February 2000 price dropped slowly. According to industry analysts priced will now increase until 2001.

The experts are bearish on RAM prices in the face of a falling Yen.

It is expected that RAM prices may be back down by this summer due to the low value of the Yen (hence the increased buying power of the US market). Over the past two decades the Yen has increased in value until its all time high in April, 1995 (see http://www.jetro.go.jp/FACTS/UA-HANDBOOK/2.html ). But since then the Yen has been loosing value topping 120 Yen to a dollar, down 48% since its post-war high in April, 1995 (see http://www.simex.com.sg/simex/chdy1.html). Moreover the Nikkei has been loosing value. Thus analyst expect prices to drop for RAM imports by this summer. Generally value changes in the Yen don't affect consumer prices for about three months.

The experts wrong about the Yen/RAM equation?

Interestingly , if you look at the value of the yen over the past ten years (see http://www.jetro.go.jp/FACTS/UA-HANDBOOK/2.html) you'll notice that the biggest RAM prices drops occurring in 1986-7 1991-2, and in 1996 correspond to periods of rapid increase in the value of the Yen. This flies in the face of conventional wisdom and must make us question whether a cheaper Yen really means cheaper RAM. Indeed looking at these data one might posit just the opposite and maybe the experts really aren't doing their homework as well as they should. Your comments are welcome on this topic.

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